The field of the invention is that of integrated circuit SRAMs.
The shrinking of MOSFET dimensions for high density, low power and enhanced performance requires reduced power supply voltages. As a result, dielectric thickness and channel length of the transistors are scaled with power supply voltage.
However, SRAM stability is severely impacted by this scaling. Small mismatches in the devices during processing can cause the cell to favor one of the states, either a 1 or a 0. Mismatches can result from dislocations between the drain and the source or from dopant implantation or thermal anneal temperature fluctuation.
The SRAM cell stability determines the soft-error and the sensitivity of the memory cell to variations in process and operating conditions. One important parameter for the stability is called “beta ratio”, which is the ratio between pull-down transistor drive current and pass-gate transistor drive current. Higher beta ratio results in better stability. However, it also results in a larger cell size. There is a trade-off between the cell area and the stability of the cell.
The art could benefit from a method to compensate and desensitize the parameters of small transistors to process fluctuations.